1. Field of the Invention
The present invention relates to a process for manufacturing a buried gate field effect transistor. Specifically, the present invention is concerned with a process for manufacturing a buried gate field effect transistor comprised of a compound semiconductor and having a Schottky junction in its V-shaped groove.
2. Description of the Prior Art
In the prior art, an increase in frequency and operational speed of a field effect transistor (FET) using a compound semiconductor, e.g., GaAs crystal, was basically achieved by shortening the gate length to increase its mutual conductance, thereby causing a decrease in the gate capacitance. In view of the fabrication technique, however, it is difficult to form a gate having a gate length of below 0.5 .mu.m.
As an example of a current attempt to shorten the effective gate length, there is known to exist a Schottky gate FET, having a V-shaped groove formed in an n-type layer at a surface of a single crystal of silicon, which is contained in the FET. This type of FET is described, for example, in Tsung D. Mok et al, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-25, No. 10, October, 1978. In this FET, a metal, such as Al, is deposited on the inner face of the V-shaped groove to form a gate electrode. The n-type region near the bottom end of the V groove acts as an effective channel in the FET. Since the bottom end of the V-shaped groove is of course pointed, the effective gate length is shortened.
In the above-mentioned FET, however, the gate electrode is formed on the entire surface of the inner wall of the V-shaped groove and this V groove is formed in the n-type single crystal layer of silicon having conductivity. The gate capacitance, therefore, becomes rather great. Further, the V groove is formed by chemical etching. However, if this V groove is formed by chemical etching, it becomes impossible to control the depth of the groove with a high degree of reproducibility. For this reason, the depth of the V groove varies with each treated wafer and, accordingly, the threshold voltage of FET also varies according to wafer. Thus, disadvantage is brought about in the prior art process.
Further, even when such FET has no V groove, the threshold voltage of FET using the n-type single crystalline layer at the surface as a channel is low in reproducibility, since that threshold voltage is substantially determined during the process of forming the n-type surface crystal.